1. Field of the Invention
The present invention relates to a multi-thread processor and its interrupt processing method.
2. Description of Related Art
In recent years, multi-thread processors have been proposed in order to improve the processing power of processors. A multi-thread processor has a plurality of hardware threads each of which generates an independent instruction flow. Further, the multi-thread processor performs arithmetic processing while changing the instruction flow to be processed in the arithmetic circuit that processes instructions in pipeline processing between a plurality of instruction flows that are generated by the respective plurality of hardware threads.
At this point, the multi-thread processor can execute an instruction generated by one hardware thread in one execution stage of the pipeline while executing an instruction generated by another hardware thread in another execution stage. That is, in the arithmetic circuit of the multi-thread processor, instructions that are independent of each other are executed in different execution stages from each other. In this way, the multi-thread processor can process each instruction flow smoothly while reducing the time period during which no instruction is processed in an execution stage of the pipeline, and thus improving the processing power of the processor.
Japanese Unexamined Patent Application Publication No. 2006-146641 discloses a technique in which when a second interruption occurs while a first interruption is being processed in a multi-thread processor, the second interrupt processing is assigned to a different hardware thread from the hardware thread executing the first interrupt processing.